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Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence Spectre with a supply voltage of 1.8V resulting in a 20% reduction in power with a higher frequency of operation compared to the reference PLL architecture. The capture range and lock range of the proposed PLL are 2.09 to 2.14 GHz and 1 to 3.5GHz, respectively. The designed PLL consumes less power and operates at a higher frequency.
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